Analysis of Underlap Strained Silicon on Insulator MOSFET for Accurate and Compact Modeling

Recently, transistors with an underlapped gate structure have been widely studied to overcome several challenges associated nanoscale devices. In this work, underlap region is incorporated at source and drain (S/D) ends in a fully depleted Strained Silicon On Insulator (SSOI) device, high-k dielectric material the spacer region. The S/D helps reduce leakage current can be particularly useful for low power applications. However, increased length degrades ON significantly. We show that issue mitigated via inclusion of spacer, which improves by enhancing controllability over channel It achieve essential requirement applications i.e. high ON/OFF ratio extremely value current. strained silicon used further improve A compact threshold voltage model developed proposed device (underlap-SSOI) while maintaining accuracy par TCAD simulations. This incorporates length, strain-induced offsets constant. may circuit